Hi Dave and thanks for taking care!
please let me explain how I came to this point: (using IAR EWARM; Cortex M4 – AT91SAM4S)
1.) NVIC
SetPriority(28, 11); // set somewhere at start; value visible in NVICIP29
2.) then PIOBIrq is fired
3.) and PIOB_IrqHandler is called
4.) some MessageProcessing is done and via xQueueSendToFrontFromISR() …
5.) … in vPortValidateInterruptPriority():
__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );
ulCurrentInterrupt is derived as 28 (0x1C).
Perfect as it fits to __vector_table[28] == PIOB_IrqHandler() :)
6.) Status at this point in time:
* 0xE000E3F0: it contains (uint8
t)0x00
* 0xE000E400: it contains (uint8t)0x00
* 0xE000E40C: it contains (uint8_t)0x00 (this is pcInterruptPriorityRegisters[ulCurrentInterrupt])
But:
* 0xE000E41C: contains (uint8t)176 (0xB0) // (11 << 4) from (step 1.)
and this is exactely: 0xE000E3F0 plus 16 + 28 == 0xE000E41C
pcInterruptPriorityRegisters[portFIRSTUSER
INTERRUPTNUMBER + ulCurrentInterrupt]
This is as I could see it in the debugger …
Indeed: if portNVIC
IPREGISTERS
OFFSET16
would not be pointing to 0xE000E3F0, but to 0xE000E400 (the real start of the NVIC_IP) then pcInterruptPriorityRegisters[ulCurrentInterrupt] would be fine as well.
Maybe you can help me to get the knot out of my brain? 😉
Kind regards, Stephan