Raising BASEPRI on M7 port (v9.0.0) is done as below:
~~~
define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()
static portFORCE_INLINE void vPortRaiseBASEPRI( void )
{
uint32
t ulNewBASEPRI = configMAXSYSCALL
INTERRUPTPRIORITY;
__asm
{
/* Set BASEPRI to the max syscall priority to effect a critical
section. */
cpsid i
msr basepri, ulNewBASEPRI
dsb
isb
cpsie i
}
}
~~~
Could you explain the need for a DSB?
Additionally, I understand that ISB is used to ensure that when this function returns, the BASEPRI change is observed. However this makes sense only if ISB is placed after “cpsie i” instruction so that the PRIMASK clear is also observed.
I have also looked into this (http://infocenter.arm.com/help/topic/com.arm.doc.dai0321a/DAI0321A
programmingguide
memorybarriers
form_profile.pdf) but I could not find the exact case in the guidelines.