Has any one worked with the
Altera Cyclone V SoC RTOS Demo ?
I’m writing a +TCP driver for the Cyclone V SoC. I want to use the HPS with Cortex-A9 and its peripherals, and I’m using mentioned demo as a start.
The EMAC and UART work fine, both transmission and reception, except that I never see any RX- or TX-interrupt occurring.
I am following these steps:
~~~
vRegisterIRQHandler( ALT
INTINTERRUPT
EMAC1IRQ, vEMACIntHandler, ( void *)&xEMACif );
alt_int_dist_priority_set( ALT_INT_INTERRUPT_EMAC1_IRQ, EMAC_INT_PRIOITY );
alt_int_dist_enable( ALT_INT_INTERRUPT_EMAC1_IRQ );
alt_int_dist_enable( ALT_INT_INTERRUPT_UART0 );
vRegisterIRQHandler( ALT_INT_INTERRUPT_UART0, vUARTIntHandler, ( void *)pxUARTHandle );
alt_int_dist_priority_set( ALT_INT_INTERRUPT_UART0, UART_INT_PRIOITY );
~~~
and I also set the peripheral’s IER (Interrupt Enable) bits for TX, RX and other events.
But the generic interrupt dispatcher,
vApplicationIRQHandler()
is only ever called for the FreeRTOS clock-tick, interrupt nr 29.
Is there a step that I missed somewhere?